PIC18F4539T-E/ML【PDF 109/322 页】IC PIC MCU FLASH 12KX16 44QFN

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 195

PIC18FXX39

20.0 SPECIAL FEATURES OF THE

CPU

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power saving Operating

modes and offer code protection. These are:

OSC Selection

RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

Interrupts

Watchdog Timer (WDT)

SLEEP

Code Protection

ID Locations

In-Circuit Serial Programming

All PIC18FXX39 devices have a Watchdog Timer,

which is permanently enabled via the configuration bits,

or software controlled. It runs off its own RC oscillator

for added reliability. There are two timers that offer nec-

essary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

RESET until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a fixed

delay on power-up only, designed to keep the part in

RESET while the power supply stabilizes. With these

two timers on-chip, most applications need no external

RESET circuitry.

SLEEP mode is designed to offer a very low current

Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

Wake-up or through an interrupt. Several oscillator

options are also made available to allow the part to fit

the application. The RC oscillator option saves system

cost, while the LP crystal option saves power. A set of

configuration bits are used to select various options.

20.1

Configuration Bits

The configuration bits can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h - 3FFFFFh),

which can only be accessed using Table Reads and

Table Writes.

Programming the configuration registers is done in a

manner similar to programming the FLASH memory

(see Section 5.5.1). The only difference is the configu-

ration registers are written a byte at a time. The

sequence of events for programming configuration

registers is:

Load table pointer with address of configuration

Write a single byte using the TBLWT instruction.

Set EEPGD to point to program memory, set the

CFGS bit to access configuration registers, and

set WREN to enable byte writes.

Disable interrupts.

Write 55h to EECON2.

Write AAh to EECON2.

Set the WR bit. This will begin the write cycle.

CPU will stall for duration of write (approximately

2 ms using internal timer).

Execute a NOP.

10. Re-enable interrupts.

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